도와주세요!!
2002.08.08 10:12:19 (*.252.62.50)
8019
안녕하세요....ezboard를 이용하고 있는 초보 학생입니다...
이틀째 ezboard 에서 led 깜빡이는 것이 안되고 있어 다른 것을 진행을
못하고 있네요..꼭 알려주세요....전 그냥...리눅스로 들어 가지 않고..
들어 가기전에 스페이스바를 눌러..ezboot 상태에서 작업을해 오고 있습니다.
프로그램은 sdt2.51을 이용해서 rom 파일을 만들었구여....이것으로...
sdram 0xc0000000 번지에 파일을 전송해서 그 번지에서 시작을 하네요..~~
실행이...go 0xc0000000 이렇게 하는거 맞지 않나요..??? 완전 초보 질문..^^
그런데 led 에 아무런....반응이 없으니...~~~ 넘 이상 하더군여...
잘못된게 없는듯 한데...왜 이런건지..??
소스를 같이 올립니다. 봐주세요...~~
맨끝부분이 led on/off coding 이구여 나머지는 init 해주는 부분이네요..~
그럼 빠른 답변 바랍니다...급한데....잘 안되네요...~~~
(소스)
;
; The AREA must have the attribute READONLY, otherwise the linker will
not
; place it in ROM.
;
; The AREA must have the attribute CODE, otherwise the assembler will not
; let us put any code in this AREA
;
; Note the '|' character is used to surround any symbols which contain
; non standard characters like '!'.
GET sa1110_def.s
AREA Init, CODE, READONLY
; Now some standard definitions...
Mode_USR EQU 0x10
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
I_Bit EQU 0x80
F_Bit EQU 0x40
; GPIO pin description
LED EQU 0x000000ff
;LED1 EQU 0x00000000
;LED2 EQU 0x00000000
;LED3 EQU 0x00000000
;LED4 EQU 0x00000000
; Locations of various things in our memory system
RAM_Base EQU 0xC0000000 ; 64k RAM at this base
RAM_Limit EQU 0xC2000000
IRQ_Stack EQU RAM_Limit ; 1K IRQ stack at top of memory
SVC_Stack EQU RAM_Limit-1024 ; followed by SVC stack
USR_Stack EQU SVC_Stack-1024 ; followed by USR stack
; --- Define entry point
EXPORT __main ; defined to ensure that C runtime system
__main ; is not linked in
ENTRY
; --- Setup interrupt / exception vectors
IF :DEF: ROM_AT_ADDRESS_ZERO
; If the ROM is at address 0 this is just a sequence of branches
B Reset_Handler
B Undefined_Handler
B SWI_Handler
B Prefetch_Handler
B Abort_Handler
NOP ; Reserved vector
B IRQ_Handler
B FIQ_Handler
ELSE
; Otherwise we copy a sequence of LDR PC instructions over the vectors
; (Note: We copy LDR PC instructions because branch instructions
; could not simply be copied, the offset in the branch instruction
; would have to be modified so that it branched into ROM. Also, a
; branch instructions might not reach if the ROM is at an address
; > 32M).
MOV R8, #0
ADR R9, Vector_Init_Block
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
; Now fall into the LDR PC, Reset_Addr instruction which will continue
; execution at 'Reset_Handler'
Vector_Init_Block
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SWI_Addr DCD SWI_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
DCD 0 ; Reserved vector
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
ENDIF
; The following handlers do not do anything useful in this example.
;
Undefined_Handler
B Undefined_Handler
SWI_Handler
B SWI_Handler
Prefetch_Handler
B Prefetch_Handler
Abort_Handler
B Abort_Handler
IRQ_Handler
B IRQ_Handler
FIQ_Handler
B FIQ_Handler
; The RESET entry point
Reset_Handler
; --- Initialise stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MOV R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =IRQ_Stack
; Set up other stack pointers if necessary
; ...
; Set up the SVC stack pointer last and return to SVC mode
MOV R0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =SVC_Stack
; --- Initialize memory controller
;************************************************************************
********************
ldr r3, = OSCR ; reset the OS Timer
Count to zero
mov r2, #0
str r2, [r3]
ldr r3, = OSMR0 ; set the Match register
to delay for 200usec
mov r2, #0x300
str r2, [r3]
ldr r3, = OSSR ; clear the status
register
mov r2, #0xF
str r2, [r3]
ldr r3, = OIER ; set bit for match
channel 0
mov r2, #0x1
str r2, [r3]
wait_200us ; ** Dev Manual
10.2.1 step 1
ldr r3, = OSSR ; use internal clock
for delay so SDCLK will stabilize
ldr r2, [r3]
tst r2, #1
beq wait_200us
; ** Dev Manual 10.2.1 step3
; NOTE: This step is for sleep reset only
; ** Dev Manual 10.2.1 step 4
ldr r3, = MDREFR ; changes states in figure 10-4
ldr r2, [r3]
orr r2, r2, #0x00200000
str r2, [r3] ; change state to Self
refresh
eor r2, r2, #0x80000000
str r2, [r3] ; change state to Pwr
Down
orr r2, r2, #0x00100000
eor r2, r2, #0x00200000
str r2, [r3] ; change state to
PWRDWNX
nop
nop ; change state to Idle
by not setting SLFRSH
; ** Dev Manual 10.2.1 step 5
ldr r3, = MDCAS00 ; dram cas wave form for dram banks
0/1
ldr r2, =0x55555557;AAAAAA7f;9f;a7;9f;7F
str r2, [r3]
ldr r3, = MDCAS01 ; dram cas wave form for dram banks
0/1
ldr r2, =0xAAAAAAAA
str r2, [r3]
ldr r3, = MDCAS02 ; dram cas wave form for dram banks
0/1
ldr r2, =0xAAAAAAAA
str r2, [r3]
ldr r3, = MDCAS20 ; dram cas wave form for dram banks
2/3
ldr r2, =0x00000000
str r2, [r3]
ldr r3, = MDCAS21 ; dram cas wave form for dram banks
2/3
ldr r2, =0x00000000
str r2, [r3]
ldr r3, = MDCAS22 ; dram cas wave form for dram banks
2/3
ldr r2, =0x00000000
str r2, [r3]
ldr r3, = MDREFR ; DRAM refresh control register
(200MHz) (103 bus)
ldr r2, =0x00700191
str r2, [r3]
ldr r3, = MDCNFG ; dram config -- dram disabled
ldr r2, =0x0000B244
str r2, [r3]
ldr r3, = PSSR ; see PSSR:DH & PH bit in Power
Manager Sleep Status Reg
mov r2, #0x18
str r2, [r3]
ldr r3, = SDRAM_B0 ; ** Dev Manual 10.2.1 step 6
mov r2, #8 ; now must do 8 refresh or
CBR commands before the first access
CBR_refresh
str r3, [r3]
subs r2, r2, #1
bne CBR_refresh
; ** Dev Manual 10.2.1 step 7
ldr r3, = MDCNFG ; dram config -- dram enable
ldr r2, [r3]
orr r2, r2, #0x00000001 ; enable appropriate
banks
str r2, [r3]
; ** Static Memory configuration
ldr r3, = MSC0 ; static memory control register
1
ldr r2, =0x00006b50;6770
str r2, [r3]
;************************************************************************
********************
; --- Initialise critical IO devices
; ...
; --- Initialise interrupt system variables here
; ...
; --- Enable interrupts
; Now safe to enable interrupts, so do this and remain in SVC mode
MOV R0, #Mode_SVC:OR:F_Bit ; Only IRQ enabled
MSR CPSR_c, R0
; --- Initialise memory required by C code
; --- Now change to user mode and set up user mode stack.
MOV R0, #Mode_USR:OR:I_Bit:OR:F_Bit
MSR CPSR_c, R0
LDR sp, =USR_Stack
; --- led on/off asm coding
START
LDR r0, =GPDR
; set GPIO direction
LDR r1, =LED
STR r1, [r0]
LDR r0, =GPSR
LDR r1, =GPCR
LED_INIT
LDR r2, =LED
LED_ON
; LED1 is on
STR r2, [r0]
; all LED is off
BL DELAY
BL DELAY
STR r2,[r1]
BL DELAY
BL DELAY
B LED_ON
DELAY
LDR r12, =0x0001FFFF
DELAY_LOOP
SUBS R12, R12, #1
; Z Flag = if Rd==0 then 1 else 0
BNE DELAY_LOOP
MOV PC, LR
END
이틀째 ezboard 에서 led 깜빡이는 것이 안되고 있어 다른 것을 진행을
못하고 있네요..꼭 알려주세요....전 그냥...리눅스로 들어 가지 않고..
들어 가기전에 스페이스바를 눌러..ezboot 상태에서 작업을해 오고 있습니다.
프로그램은 sdt2.51을 이용해서 rom 파일을 만들었구여....이것으로...
sdram 0xc0000000 번지에 파일을 전송해서 그 번지에서 시작을 하네요..~~
실행이...go 0xc0000000 이렇게 하는거 맞지 않나요..??? 완전 초보 질문..^^
그런데 led 에 아무런....반응이 없으니...~~~ 넘 이상 하더군여...
잘못된게 없는듯 한데...왜 이런건지..??
소스를 같이 올립니다. 봐주세요...~~
맨끝부분이 led on/off coding 이구여 나머지는 init 해주는 부분이네요..~
그럼 빠른 답변 바랍니다...급한데....잘 안되네요...~~~
(소스)
;
; The AREA must have the attribute READONLY, otherwise the linker will
not
; place it in ROM.
;
; The AREA must have the attribute CODE, otherwise the assembler will not
; let us put any code in this AREA
;
; Note the '|' character is used to surround any symbols which contain
; non standard characters like '!'.
GET sa1110_def.s
AREA Init, CODE, READONLY
; Now some standard definitions...
Mode_USR EQU 0x10
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
I_Bit EQU 0x80
F_Bit EQU 0x40
; GPIO pin description
LED EQU 0x000000ff
;LED1 EQU 0x00000000
;LED2 EQU 0x00000000
;LED3 EQU 0x00000000
;LED4 EQU 0x00000000
; Locations of various things in our memory system
RAM_Base EQU 0xC0000000 ; 64k RAM at this base
RAM_Limit EQU 0xC2000000
IRQ_Stack EQU RAM_Limit ; 1K IRQ stack at top of memory
SVC_Stack EQU RAM_Limit-1024 ; followed by SVC stack
USR_Stack EQU SVC_Stack-1024 ; followed by USR stack
; --- Define entry point
EXPORT __main ; defined to ensure that C runtime system
__main ; is not linked in
ENTRY
; --- Setup interrupt / exception vectors
IF :DEF: ROM_AT_ADDRESS_ZERO
; If the ROM is at address 0 this is just a sequence of branches
B Reset_Handler
B Undefined_Handler
B SWI_Handler
B Prefetch_Handler
B Abort_Handler
NOP ; Reserved vector
B IRQ_Handler
B FIQ_Handler
ELSE
; Otherwise we copy a sequence of LDR PC instructions over the vectors
; (Note: We copy LDR PC instructions because branch instructions
; could not simply be copied, the offset in the branch instruction
; would have to be modified so that it branched into ROM. Also, a
; branch instructions might not reach if the ROM is at an address
; > 32M).
MOV R8, #0
ADR R9, Vector_Init_Block
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
LDMIA R9!, {R0-R7}
STMIA R8!, {R0-R7}
; Now fall into the LDR PC, Reset_Addr instruction which will continue
; execution at 'Reset_Handler'
Vector_Init_Block
LDR PC, Reset_Addr
LDR PC, Undefined_Addr
LDR PC, SWI_Addr
LDR PC, Prefetch_Addr
LDR PC, Abort_Addr
NOP
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SWI_Addr DCD SWI_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
DCD 0 ; Reserved vector
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
ENDIF
; The following handlers do not do anything useful in this example.
;
Undefined_Handler
B Undefined_Handler
SWI_Handler
B SWI_Handler
Prefetch_Handler
B Prefetch_Handler
Abort_Handler
B Abort_Handler
IRQ_Handler
B IRQ_Handler
FIQ_Handler
B FIQ_Handler
; The RESET entry point
Reset_Handler
; --- Initialise stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MOV R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =IRQ_Stack
; Set up other stack pointers if necessary
; ...
; Set up the SVC stack pointer last and return to SVC mode
MOV R0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR CPSR_c, R0
LDR R13, =SVC_Stack
; --- Initialize memory controller
;************************************************************************
********************
ldr r3, = OSCR ; reset the OS Timer
Count to zero
mov r2, #0
str r2, [r3]
ldr r3, = OSMR0 ; set the Match register
to delay for 200usec
mov r2, #0x300
str r2, [r3]
ldr r3, = OSSR ; clear the status
register
mov r2, #0xF
str r2, [r3]
ldr r3, = OIER ; set bit for match
channel 0
mov r2, #0x1
str r2, [r3]
wait_200us ; ** Dev Manual
10.2.1 step 1
ldr r3, = OSSR ; use internal clock
for delay so SDCLK will stabilize
ldr r2, [r3]
tst r2, #1
beq wait_200us
; ** Dev Manual 10.2.1 step3
; NOTE: This step is for sleep reset only
; ** Dev Manual 10.2.1 step 4
ldr r3, = MDREFR ; changes states in figure 10-4
ldr r2, [r3]
orr r2, r2, #0x00200000
str r2, [r3] ; change state to Self
refresh
eor r2, r2, #0x80000000
str r2, [r3] ; change state to Pwr
Down
orr r2, r2, #0x00100000
eor r2, r2, #0x00200000
str r2, [r3] ; change state to
PWRDWNX
nop
nop ; change state to Idle
by not setting SLFRSH
; ** Dev Manual 10.2.1 step 5
ldr r3, = MDCAS00 ; dram cas wave form for dram banks
0/1
ldr r2, =0x55555557;AAAAAA7f;9f;a7;9f;7F
str r2, [r3]
ldr r3, = MDCAS01 ; dram cas wave form for dram banks
0/1
ldr r2, =0xAAAAAAAA
str r2, [r3]
ldr r3, = MDCAS02 ; dram cas wave form for dram banks
0/1
ldr r2, =0xAAAAAAAA
str r2, [r3]
ldr r3, = MDCAS20 ; dram cas wave form for dram banks
2/3
ldr r2, =0x00000000
str r2, [r3]
ldr r3, = MDCAS21 ; dram cas wave form for dram banks
2/3
ldr r2, =0x00000000
str r2, [r3]
ldr r3, = MDCAS22 ; dram cas wave form for dram banks
2/3
ldr r2, =0x00000000
str r2, [r3]
ldr r3, = MDREFR ; DRAM refresh control register
(200MHz) (103 bus)
ldr r2, =0x00700191
str r2, [r3]
ldr r3, = MDCNFG ; dram config -- dram disabled
ldr r2, =0x0000B244
str r2, [r3]
ldr r3, = PSSR ; see PSSR:DH & PH bit in Power
Manager Sleep Status Reg
mov r2, #0x18
str r2, [r3]
ldr r3, = SDRAM_B0 ; ** Dev Manual 10.2.1 step 6
mov r2, #8 ; now must do 8 refresh or
CBR commands before the first access
CBR_refresh
str r3, [r3]
subs r2, r2, #1
bne CBR_refresh
; ** Dev Manual 10.2.1 step 7
ldr r3, = MDCNFG ; dram config -- dram enable
ldr r2, [r3]
orr r2, r2, #0x00000001 ; enable appropriate
banks
str r2, [r3]
; ** Static Memory configuration
ldr r3, = MSC0 ; static memory control register
1
ldr r2, =0x00006b50;6770
str r2, [r3]
;************************************************************************
********************
; --- Initialise critical IO devices
; ...
; --- Initialise interrupt system variables here
; ...
; --- Enable interrupts
; Now safe to enable interrupts, so do this and remain in SVC mode
MOV R0, #Mode_SVC:OR:F_Bit ; Only IRQ enabled
MSR CPSR_c, R0
; --- Initialise memory required by C code
; --- Now change to user mode and set up user mode stack.
MOV R0, #Mode_USR:OR:I_Bit:OR:F_Bit
MSR CPSR_c, R0
LDR sp, =USR_Stack
; --- led on/off asm coding
START
LDR r0, =GPDR
; set GPIO direction
LDR r1, =LED
STR r1, [r0]
LDR r0, =GPSR
LDR r1, =GPCR
LED_INIT
LDR r2, =LED
LED_ON
; LED1 is on
STR r2, [r0]
; all LED is off
BL DELAY
BL DELAY
STR r2,[r1]
BL DELAY
BL DELAY
B LED_ON
DELAY
LDR r12, =0x0001FFFF
DELAY_LOOP
SUBS R12, R12, #1
; Z Flag = if Rd==0 then 1 else 0
BNE DELAY_LOOP
MOV PC, LR
END
